Reconfigurable hardware revisited : implementing an optimised AI pipeline on the HPDP processor

Tordoya Taquichiri, Carlos Rafael; Ganz, David; Buchheim, Klaus

Publication type:	Conference other
Type of review:	Peer review (abstract)
Title:	Reconfigurable hardware revisited : implementing an optimised AI pipeline on the HPDP processor
Authors:	Tordoya Taquichiri, Carlos Rafael Ganz, David Buchheim, Klaus
et. al:	No
Conference details:	Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024
Issue Date:	28-May-2024
Language:	English
Subjects:	Artificial Intelligence (AI); Pipeline; Acceleration; High Performance Data Processor (HPDP); Performance; Radiation; Processor; Space
Subject (DDC):	006: Special computer methods
Abstract:	The space application domain demands robust and dependable hardware, often necessitating the use of radiation-hardened (rad-hardened) components, notably processors and memory. This limitation poses challenges when implementing modern algorithms, particularly those with high computational complexity such as AI-based classification, within real-time constraints. This paper introduces the High Performance Data Processor (HPDP-40), a unique radiation-hardened co-processor designed for space applications. The HPDP-40 features low power consumption, runtime reconfigurability, and a compact form, making it suitable for computationally intensive tasks. To address the constraints imposed by rad-hardened components, we propose deploying the HPDP-40 in conjunction with an optimized AI-pipeline. Despite successful testing on AI applications, a lack of a generic AI framework for the HPDP limits broader implementation. This paper presents an implementation effort involving the porting of an optimized AI-pipeline to the HPDP-40, showcasing the structured partitioning of the pipeline and its mapping across various processors and functional units. The proposed solution offers a streamlined approach to deploying AI models on the HPDP-40, as it leverages compatibility with major AI frameworks and eliminates the need for specific HPDP coding. This not only simplifies the integration process but also opens avenues for AI applications in future European Space Agency (ESA) missions with stringent availability requirements, such as landers and deep space robotics. The presented hardware/software stack could contribute to reinforcing Europe's capability to utilize AI effectively in space exploration. The paper concludes with performance measurements, insights, and recommendations for future work in this promising intersection of space technology and artificial intelligence.
URI:	https://digitalcollection.zhaw.ch/handle/11475/30808
Fulltext version:	Published version
License (according to publishing contract):	Licence according to publishing contract
Departement:	School of Engineering
Organisational Unit:	Institute of Embedded Systems (InES)
Appears in collections:	Publikationen School of Engineering

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Tordoya Taquichiri, C. R., Ganz, D., & Buchheim, K. (2024, May 28). Reconfigurable hardware revisited : implementing an optimised AI pipeline on the HPDP processor. Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024.

Tordoya Taquichiri, C.R., Ganz, D. and Buchheim, K. (2024) ‘Reconfigurable hardware revisited : implementing an optimised AI pipeline on the HPDP processor’, in Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024.

C. R. Tordoya Taquichiri, D. Ganz, and K. Buchheim, “Reconfigurable hardware revisited : implementing an optimised AI pipeline on the HPDP processor,” in Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024, May 2024.

TORDOYA TAQUICHIRI, Carlos Rafael, David GANZ und Klaus BUCHHEIM, 2024. Reconfigurable hardware revisited : implementing an optimised AI pipeline on the HPDP processor. In: Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024. Conference presentation. 28 Mai 2024

Tordoya Taquichiri, Carlos Rafael, David Ganz, and Klaus Buchheim. 2024. “Reconfigurable Hardware Revisited : Implementing an Optimised AI Pipeline on the HPDP Processor.” Conference presentation. In Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024.

Tordoya Taquichiri, Carlos Rafael, et al. “Reconfigurable Hardware Revisited : Implementing an Optimised AI Pipeline on the HPDP Processor.” Embedded Computing Conference (ECC), Winterthur, Switzerland, 28 May 2024, 2024.