Efficient mapping of neural networks on FPGA with generated VHDL code

Delafontaine, Thierry; Rosenthal, Matthias

Publication type:	Conference other
Type of review:	No review
Title:	Efficient mapping of neural networks on FPGA with generated VHDL code
Authors:	Delafontaine, Thierry Rosenthal, Matthias
et. al:	Yes
Conference details:	European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023
Issue Date:	17-Oct-2023
Language:	English
Subjects:	FPGA; AI; Accelerator; Edge AI
Subject (DDC):	006: Special computer methods
Abstract:	FPGAs are an ideal platform to accelerate AI processing at the edge. However, simple toolchains are lacking to deploy AI networks directly on the FPGA. We present a framework that allows the design of custom AI accelerators for FPGAs by generating application application-specific HDL code. Unlike other solutions, the framework proposes a dataflow-style hardware mapping at the RTL level that is specific to the neural network and makes optimal use of available resources. We focused on providing an easy-to-use interface and extensible core that allows developers to add custom operators, optimizers, objectives, metrics, and callbacks.
URI:	https://digitalcollection.zhaw.ch/handle/11475/29035
Fulltext version:	Published version
License (according to publishing contract):	Not specified
Departement:	School of Engineering
Organisational Unit:	Institute of Embedded Systems (InES)
Appears in collections:	Publikationen School of Engineering

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Delafontaine, T., & Rosenthal, M. (2023, October 17). Efficient mapping of neural networks on FPGA with generated VHDL code. European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023.

Delafontaine, T. and Rosenthal, M. (2023) ‘Efficient mapping of neural networks on FPGA with generated VHDL code’, in European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023.

T. Delafontaine and M. Rosenthal, “Efficient mapping of neural networks on FPGA with generated VHDL code,” in European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023, Oct. 2023.

DELAFONTAINE, Thierry und Matthias ROSENTHAL, 2023. Efficient mapping of neural networks on FPGA with generated VHDL code. In: European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023. Conference presentation. 17 Oktober 2023

Delafontaine, Thierry, and Matthias Rosenthal. 2023. “Efficient Mapping of Neural Networks on FPGA with Generated VHDL Code.” Conference presentation. In European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023.

Delafontaine, Thierry, and Matthias Rosenthal. “Efficient Mapping of Neural Networks on FPGA with Generated VHDL Code.” European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023, 2023.