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dc.contributor.authorDelafontaine, Thierry-
dc.contributor.authorRosenthal, Matthias-
dc.date.accessioned2023-11-10T17:34:18Z-
dc.date.available2023-11-10T17:34:18Z-
dc.date.issued2023-10-17-
dc.identifier.urihttps://digitalcollection.zhaw.ch/handle/11475/29035-
dc.description.abstractFPGAs are an ideal platform to accelerate AI processing at the edge. However, simple toolchains are lacking to deploy AI networks directly on the FPGA. We present a framework that allows the design of custom AI accelerators for FPGAs by generating application application-specific HDL code. Unlike other solutions, the framework proposes a dataflow-style hardware mapping at the RTL level that is specific to the neural network and makes optimal use of available resources. We focused on providing an easy-to-use interface and extensible core that allows developers to add custom operators, optimizers, objectives, metrics, and callbacks.de_CH
dc.language.isoende_CH
dc.rightsNot specifiedde_CH
dc.subjectFPGAde_CH
dc.subjectAIde_CH
dc.subjectAcceleratorde_CH
dc.subjectEdge AIde_CH
dc.subject.ddc006: Spezielle Computerverfahrende_CH
dc.titleEfficient mapping of neural networks on FPGA with generated VHDL codede_CH
dc.typeKonferenz: Sonstigesde_CH
dcterms.typeTextde_CH
zhaw.departementSchool of Engineeringde_CH
zhaw.organisationalunitInstitute of Embedded Systems (InES)de_CH
zhaw.conference.detailsEuropean Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023de_CH
zhaw.funding.euNot specifiedde_CH
zhaw.originated.zhawYesde_CH
zhaw.publication.statuspublishedVersionde_CH
zhaw.publication.reviewKeine Begutachtungde_CH
zhaw.author.additionalYesde_CH
zhaw.display.portraitYesde_CH
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Delafontaine, T., & Rosenthal, M. (2023, October 17). Efficient mapping of neural networks on FPGA with generated VHDL code. European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023.
Delafontaine, T. and Rosenthal, M. (2023) ‘Efficient mapping of neural networks on FPGA with generated VHDL code’, in European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023.
T. Delafontaine and M. Rosenthal, “Efficient mapping of neural networks on FPGA with generated VHDL code,” in European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023, Oct. 2023.
DELAFONTAINE, Thierry und Matthias ROSENTHAL, 2023. Efficient mapping of neural networks on FPGA with generated VHDL code. In: European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023. Conference presentation. 17 Oktober 2023
Delafontaine, Thierry, and Matthias Rosenthal. 2023. “Efficient Mapping of Neural Networks on FPGA with Generated VHDL Code.” Conference presentation. In European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023.
Delafontaine, Thierry, and Matthias Rosenthal. “Efficient Mapping of Neural Networks on FPGA with Generated VHDL Code.” European Conference on EDGE AI Technologies and Applications – EEAI, Athens, Greece, 17-19 October 2023, 2023.


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