Please use this identifier to cite or link to this item: https://doi.org/10.21256/zhaw-3523
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dc.contributor.authorWelti, Tobias-
dc.contributor.authorRosenthal, Matthias-
dc.date.accessioned2018-03-07T15:01:21Z-
dc.date.available2018-03-07T15:01:21Z-
dc.date.issued2018-02-28-
dc.identifier.urihttps://digitalcollection.zhaw.ch/handle/11475/3508-
dc.description.abstractWith the recent development of faster and more complex Multiprocessor System-on-Cips (MPSoCs), a large number of different resources have become available on a single chip. For example, Xilinx's UltraScale+ is a powerful MPSoC with four ARM Cortex-A53 CPUs, two Cortex-R5 real-time cores, an FPGA fabric and a Mali-400 GPU. Optimal partitioning between CPUs, real-time cores, GPU and FPGA is therefore a challenge. For many scientific applications with high sampling rates and real-time signal analysis, an FFT needs to be calculated and analyzed directly in the measuring device. The goal of partitioning such an FFT in an MPSoC is to make best use of the available resources, to minimize latency and to optimize performance. The paper compares different partitioning designs and discusses their advantages and disadvantages. Measurement results with up to 250 MSamples per second are shown.de_CH
dc.language.isoende_CH
dc.publisherWEKA FACHMEDIEN GmbHde_CH
dc.rightsLicence according to publishing contractde_CH
dc.subjectFPGAde_CH
dc.subjectMPSoCde_CH
dc.subjectPartitioningde_CH
dc.subjectUltraScale+de_CH
dc.subjectARM NEONde_CH
dc.subjectLow latency processingde_CH
dc.subjectAsymmetric multiprocessingde_CH
dc.subject.ddc004: Informatikde_CH
dc.titlePartitioning of computationally intensive tasks between FPGA and CPUsde_CH
dc.typeKonferenz: Paperde_CH
dcterms.typeTextde_CH
zhaw.departementSchool of Engineeringde_CH
zhaw.organisationalunitInstitute of Embedded Systems (InES)de_CH
zhaw.publisher.placeHaarde_CH
dc.identifier.doi10.21256/zhaw-3523de_CH
zhaw.conference.detailsEmbedded World Conference, Nürnberg, 27. Februar - 1. März 2018de_CH
zhaw.funding.euNode_CH
zhaw.originated.zhawYesde_CH
zhaw.publication.statuspublishedVersionde_CH
zhaw.publication.reviewPeer review (Abstract)de_CH
Appears in Collections:Publikationen School of Engineering

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