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https://doi.org/10.21256/zhaw-3523| Publikationstyp: | Konferenz: Paper |
| Art der Begutachtung: | Peer review (Abstract) |
| Titel: | Partitioning of computationally intensive tasks between FPGA and CPUs |
| Autor/-in: | Welti, Tobias Rosenthal, Matthias |
| DOI: | 10.21256/zhaw-3523 |
| Angaben zur Konferenz: | Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018 |
| Erscheinungsdatum: | 2018 |
| Verlag / Hrsg. Institution: | WEKA |
| Verlag / Hrsg. Institution: | Haar |
| Sprache: | Englisch |
| Schlagwörter: | FPGA; MPSoC; Partitioning; UltraScale+; ARM NEON; Low latency processing; Asymmetric multiprocessing |
| Fachgebiet (DDC): | 004: Informatik |
| Zusammenfassung: | With the recent development of faster and more complex Multiprocessor System-on-Cips (MPSoCs), a large number of different resources have become available on a single chip. For example, Xilinx's UltraScale+ is a powerful MPSoC with four ARM Cortex-A53 CPUs, two Cortex-R5 real-time cores, an FPGA fabric and a Mali-400 GPU. Optimal partitioning between CPUs, real-time cores, GPU and FPGA is therefore a challenge. For many scientific applications with high sampling rates and real-time signal analysis, an FFT needs to be calculated and analyzed directly in the measuring device. The goal of partitioning such an FFT in an MPSoC is to make best use of the available resources, to minimize latency and to optimize performance. The paper compares different partitioning designs and discusses their advantages and disadvantages. Measurement results with up to 250 MSamples per second are shown. |
| URI: | https://digitalcollection.zhaw.ch/handle/11475/3508 |
| Volltext Version: | Publizierte Version |
| Lizenz (gemäss Verlagsvertrag): | Lizenz gemäss Verlagsvertrag |
| Departement: | School of Engineering |
| Organisationseinheit: | Institute of Embedded Systems (InES) |
| Enthalten in den Sammlungen: | Publikationen School of Engineering |
Dateien zu dieser Ressource:
| Datei | Beschreibung | Größe | Format | |
|---|---|---|---|---|
| 12_Welti(submitted).pdf | Full Paper | 749.74 kB | Adobe PDF |  Öffnen/Anzeigen |
Zur Langanzeige
Welti, T., & Rosenthal, M. (2018). Partitioning of computationally intensive tasks between FPGA and CPUs. Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018. https://doi.org/10.21256/zhaw-3523
Welti, T. and Rosenthal, M. (2018) ‘Partitioning of computationally intensive tasks between FPGA and CPUs’, in Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018. Haar: WEKA. Available at: https://doi.org/10.21256/zhaw-3523.
T. Welti and M. Rosenthal, “Partitioning of computationally intensive tasks between FPGA and CPUs,” in Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018, 2018. doi: 10.21256/zhaw-3523.
WELTI, Tobias und Matthias ROSENTHAL, 2018. Partitioning of computationally intensive tasks between FPGA and CPUs. In: Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018. Conference paper. Haar: WEKA. 2018
Welti, Tobias, and Matthias Rosenthal. 2018. “Partitioning of Computationally Intensive Tasks between FPGA and CPUs.” Conference paper. In Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018. Haar: WEKA. https://doi.org/10.21256/zhaw-3523.
Welti, Tobias, and Matthias Rosenthal. “Partitioning of Computationally Intensive Tasks between FPGA and CPUs.” Embedded World Conference, Nuremberg, Germany, 27 February - 1 March 2018, WEKA, 2018, https://doi.org/10.21256/zhaw-3523.
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