Please use this identifier to cite or link to this item: https://doi.org/10.21256/zhaw-3523
Title: Partitioning of computationally intensive tasks between FPGA and CPUs
Authors : Welti, Tobias
Rosenthal, Matthias
Conference details: Embedded World Conference, Nürnberg, 27. Februar - 1. März 2018
Publisher / Ed. Institution : WEKA FACHMEDIEN GmbH
Publisher / Ed. Institution: Haar
Issue Date: 28-Feb-2018
License (according to publishing contract) : Licence according to publishing contract
Type of review: Peer review (Abstract)
Language : English
Subjects : FPGA; MPSoC; Partitioning; UltraScale+; ARM NEON; Low latency processing; Asymmetric multiprocessing
Subject (DDC) : 004: Computer science
Abstract: With the recent development of faster and more complex Multiprocessor System-on-Cips (MPSoCs), a large number of different resources have become available on a single chip. For example, Xilinx's UltraScale+ is a powerful MPSoC with four ARM Cortex-A53 CPUs, two Cortex-R5 real-time cores, an FPGA fabric and a Mali-400 GPU. Optimal partitioning between CPUs, real-time cores, GPU and FPGA is therefore a challenge. For many scientific applications with high sampling rates and real-time signal analysis, an FFT needs to be calculated and analyzed directly in the measuring device. The goal of partitioning such an FFT in an MPSoC is to make best use of the available resources, to minimize latency and to optimize performance. The paper compares different partitioning designs and discusses their advantages and disadvantages. Measurement results with up to 250 MSamples per second are shown.
Departement: School of Engineering
Organisational Unit: Institute of Embedded Systems (InES)
Publication type: Conference Paper
DOI : 10.21256/zhaw-3523
URI: https://digitalcollection.zhaw.ch/handle/11475/3508
Appears in Collections:Publikationen School of Engineering

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